1. Field of the Invention
The present invention relates to the field of digital clock signal synthesizers and, more particularly, to a synthesizer for generating multiple clock signals with improved clock pulse width and position accuracy.
2. Description of Related Art
Various systems require accurate multiple clock signals. One particular system is an imaging system that incorporates a CCD imager that has to be scanned (activated) using multiple clock signals to read out lines of charges that are a function of an image. As the frequency (speed) of operation of CCD imaging systems increase, the performance demands placed on the digital logic associated with such systems increases proportionately. Edge positioning accuracy and adjustability for clocking the CCD and operating the associated signal processing becomes critical. These adjustments are required to optimize and compensate for, clock driver performance, CCD imager or performance, and to optimize the signal processing signal to noise ratio.
One prior art approach to a synthesizer logic design for high speed CCD imager systems, is illustrated in FIG. 1. Digital counters 11, 12 and 13 are used to develop address information for elements (pixels) within a line based on an oscillator signal from an element rate oscillator 10. A fast pulse section 30 is formed with delay circuits 1-4. Each delay circuit is comprised of a selectable digital delay A, a selectable digital delay B and a NAND gate 19. That are used to control the pulse width and the position of the pulse within an element scan cycle, and to position the pulses in relation to each other. This prior art approach works, however it contains many components (requiring, for example, two digital delays A and B per clock generated), with each component consuming power.